This invention relates to the field of decoupling capacitors for integrated circuits. More particularly, this invention relates to a novel flat decoupling capacitor and a method of formation thereof which incorporates therein a multilayer chip capacitor whereby higher capacitance values are provided for integrated circuits.
Decoupling capacitors are utilized extensively in printed circuit boards for use in conjunction with dual-in-line integrated circuits or other electronic components. Prior art decoupling capacitors are described in prior U.S. patent application Ser. Nos. 403,408 and 456,654 which are assigned to the assignee hereof and incorporated herein by reference thereto.
Unfortunately, the types of decoupling capacitors disclosed in the above patent applications are limited to specific capacitance values. These values depend upon the number of individual planar ceramic capacitor chips which the decoupling capacitor is able to hold therein. Often, these limited and specific values do not meet the requirements of purchasers and manufacturers. In fact, manufacturers of electronic equipment and the like have required higher capacitance levels than can be achieved by utilizing standard planar chips. The need for higher capacitance values is particularly important for the smaller integrated circuit packages wherein only relatively low (i.e., 0.02 microfarads) capacitance levels are currently available.
It has been determined that the problem concerning limited capacitance values in decoupling capacitors cannot be overcome simply by modifying existing capacitors without great expense and substantial changes. In fact, using current technology, a conventional planar capacitor cannot be modified to attain higher capacitance without major changes in the manufacturing process. Furthermore, even with these substantial modifications, at most, only a doubling or tripling of the nominal capacitance is probably the best one skilled in the art could hope to attain.